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High Speed, Combi-SenseTM Synchronous MOSFET Driver
POWER MANAGEMENT Description
The SC1211 is a high speed, Combi-SenseTM, dual output driver designed to drive high-side and low-side MOSFETs in a synchronous Buck converter. These drivers combined with Combi-Sense PWM controllers, such as Semtech SC2643VX or SC2643, provide a cost effective multi-phase voltage regulator for advanced microprocessors. The Combi-SenseTM is a technique to sense the inductor current for peak current mode control of voltage regulator without using sensing resistor. It provides the following advantages: - No costly precision sensing resistor - Lossless current sensing - High level noise free signal - Fast response - Suitable for wide range of duty cycle - Only two small signal components (third optional) The detailed explanation of the technique can be found in the Applications Information section. A 30ns max propagation delay from input transition to the gate of the power FET's guarantees operation at high switching frequencies. Internal overlap protection circuit prevents shoot-through from Vin to PGND in the main and synchronous MOSFETs. The adaptive overlap protection circuit ensures the bottom FET does not turn on until the top FET source has reached 1V, to prevent crossconduction. 8.5V gate drive provides optimum enhancement of MOSFETs at minimum driver and MOSFET switching loss. High current drive capability allows fast switching, thus reducing switching losses at high (up to 1.5MHz) frequencies without causing thermal stress on the driver. Under-voltage-lockout and over-temperature shutdown features are included for proper and safe operation. Timed latches and improved robustness are built into the housekeeping functions such as the Under Voltage Lockout and adaptive Shoot-through protection circuitry to prevent false triggering and to assure safe operation. The SC1211 is offered in a Power SOIC-8L package.
SC1211
Features
u High efficiency u +12V supply voltage with internal LDO for optimum
gate drive
u High peak drive current u Adaptive non-overlapping gate drives provide u u u u u u u u
shoot-through protection Support Combi-SenseTM and VID-on-fly operations Fast rise and fall times (15ns typical with 3000pf load) Ultra-low (<30ns) propagation delay (BG going low) Floating top gate drive Crowbar function for over voltage protection High frequency (to 1.5 MHz) operation allows use of small inductors and low cost ceramic capacitors Under-voltage-lockout Low quiescent current
Applications
u Intel Pentium(R) processor power supplies u AMD AthlonTM and AMD-K8TM processor power supplies u High current low voltage DC-DC converters
October 12, 2003
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+12V 1 640nH R1 Q1 2R2 R14 10 4 3 2 1 VCC U1 1R0 1 2 R26 R3 900nH C5 TG CO BST DRN L2 R2 VCORE C4 D1N4148 1uF 4.7uF 4.7uF 1500uF + D1 C2 C3 C1 2
+
C13 1 OS3 U2 VIN OUTSEN OUT4 OUT3 D1N4148 R15 4 3 2 1 R18 TG CO BST DRN 10k 250k PGND VREG C23 VIN VPN 0.1uF 3.7k 5 6 VPN2 R21 BG 9 R17 U3 1R0 1 1uF OUT2 OUT1 AGND OSCREF PGOOD VID5 VID0 VID1 13 14 7 15 16 17 18 19 20 21 Q3 22 D2 C16 C17 4.7uF 23 OS2 OS1 BGOUT ERROUT GNDSEN FB DACSTEP VCC VID4 VID3 VID2 OS4 4.7uF 2 3 4 5 6 R25 optional 8 9 C22 1uF 12 11 10 7 24
R10
C12
R9 33.2k
C10 4.7nF
VCORE
C11
2.2nF
+
+
+
optional
C20
+
+
+
VID3 D1N4148 1uF R22 4 3 2 1 U4 VCORE 1R0
Q5
+
VID0
+
VREG
P4GND VPN1
C39 1nF VIN VPN BG VPN1 5 6 7 C35 4.7uF 8
100
Q6
1R0 C34 2.2nF
R24 P4GND 0R0
+
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L1 VIN
SC1211
9 C37 1nF 100 1R0 C8 C9 Q2 VPN3
VPN1 PGND C6 0.1uF VIN VPN R6 BG VPN3 5 6 7 8 R7 931 R8 301 22.1k C7 3.3nF VREG
VPN2
VPN3
1800uF/6.3V
POWER MANAGEMENT Typical Application Circuit
R4
R5
22.1k
22.1k
1800uF/6.3V
R11
4.7nF
33.2k
4.7nF
C14 1800uF/6.3V C15 1500uF + C18 1800uF/6.3V
33.2k
R12
500
VID_PWRGD
R13
R20
21.5k
R16
100k
L3 2 R27 900nH
C19 1800uF/6.3V
SC1211
C38 1nF VPN2
2
C26 8
C21
1uF
C36
R19 100 Q4 1R0 C25 2.2nF
470pF
0.1uF
C24 1800uF/6.3V
C27 4.7uF VIN C29 1800uF/6.3V
PGOOD
SC2643VX
VID5 D3 C30
VID4
C31 4.7uF
C28 1500uF
+
1800uF/6.3V
VID2
VID1
C32 1800uF/6.3V L4 1 2 TG CO BST DRN PGND
SC1211
9
R28 R23
900nH
C33 1800uF/6.3V
SC1211
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SC1211
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter VI N Supply Voltage BST to DRN TG to DRN TG to DRN Pulse BST to PGND BST to PGND Pulse DRN to PGND DRN to PGND Pulse BG to PGND BG to PGND Pulse VREG to PGND VPN to PGND VPN to PGND Pulse PWM Input Continuous Pow er Dissipation Thermal Resistance Junction to Case Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 Sec.
Symbol VI N VBST-DRN VTG-DRN VTG-DRN-PULSE VBST-PGND VBST-GND-PULSE VDRN-PGND VDRN-PGND-PULSE VBG-PGND VBG-PGND-PULSE VREG-PGND VPN VPN-PULSE CO PD JC TJ TSTG TLEAD
Conditions
Maximum 16 11 -0.3 to 11
Units V V V V V V V V V V V V V V V W C/W C C C
VPEAK, tPULSE < 20ns
(2)
-2 40
tPULSE < 100ns
45 -2 to 30
VPEAK, tPULSE < 200ns (2) VPEAK, tPULSE < 20ns (2)
-5 to 35 -VREG to 35 -0.3 to 11
VPEAK, tPULSE < 20ns
(2)
-3.5 11 16
tPULSE < 100ns
20 -0.3 to 8.5
TA = 25C, TJ =125C
2.56 8 0 to +150 -65 to +150 300
NOTE: (1). This device is ESD sensitive. Use of standard ESD handling precautions is required. (2). Pulse width measured from 50% to 50% of peak voltage VPEAK.
Electrical Characteristics
Unless specified: TA = 25C; VIN = 12V; VREG = 8.5V
Parameter Pow er Supply Supply Voltage Qui escent C urrent, Operati ng U nder Voltage Lockout Start Threshold of VREG Voltage Hysteresi s Internal LD O LD O Output D rop Out Voltage
Symbol
C onditions
Min
Typ
Max
U nits
VI N Iq_op
9
12 3.0
15
V mA
VREG_START VhysUVLO
4 160
4.3
V mV
VREG VDROP
VI N = 9V to 15V VI N = 5V to 8.8V
8.5 0.3
V V
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SC1211
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: TA = 25C; VIN = 12V; VREG = 8.5V
Parameter CO Logic High Input Voltage Logic Low Input Voltage T hermal Shutdown Over Temperature Trip Point Hysteresis High Side Driver (T G) Output Impedance Rise Time Fall Time Propagation Delay, TG Going High Propagation Delay, TG Going Low Low-Side Driver (BG) Output Impedance Rise Time Fall Time Propagation Delay, BG Going High Propagation Delay, BG Going Low BG Minimum Off-time (1) Under-Voltage-Lockout T ime Delay VREG ramping up VREG ramping down
Symbol
Conditions
Min
Typ
Max
Units
VCO_H VCO_L
2.0 0.8
V V
TOTP THYST
155 10
C C
RSRC_TG RSINK_TG tR_TG tF_TG tPDH_TG tPDL_TG
1.5 VBST - VDRN = 8.5V CL = 3.3nF, VBST - VDRN = 8.5V CL = 3.3nF, VBST - VDRN = 8.5V VBST - VDRN = 8.5V VBST - VDRN = 8.5V 1.0 15 10 37 30
3.0 2.0
ns ns ns ns
RSRC_BG RSINK_BG tR_BG tF_BG tPDH_BG tPDL_BG tOFF_BG
VREG = 8.5V CL = 3.3nF, VREG = 8.5V CL = 3.3nF, VREG = 8.5V VREG = 8.5V VREG = 8.5V
1.5 1.5 10 10 20 27 75
3.0 3.0
ns ns ns ns ns
tPDH_UVLO tPDL_UVLO
2 2
s s
NOTE: (1) Guaranteed by design.
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SC1211
POWER MANAGEMENT Timing Diagrams
CO
DRN
1.0V
TG tPDH_TG tR_TG tPDL_TG tF_TG
BG tPDL_BG tF_BG
1.4V
tPDH_BG
tR_BG
Rising Edge Transition
Falling Edge Transition
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SC1211
POWER MANAGEMENT Pin Configuration
Top View
Ordering Information
Device
(1)
P ackag e EDP SO-8
Temp Range (TJ) 0 to 125C
SC1211STR
DRN TG BST CO
1
PGND
8 7 6 5
BG VREG VIN VPN
2 3 4
Note: (1) Only available in tape and reel packaging. A reel contains 2500 devices.
EXPOSED PAD MUST BE SOLDERED TO POWER GROUND PLANE
(Power SOIC-8)
Pin Descriptions
Pin # 1 2 3 4 5 6 7 8 PAD Pin N ame D RN TG BST CO VPN VIN VREG BG PGND Pin Function The power phase node (or swi tchi ng node) of the synchronous buck converter. Thi s pi n can be subjected to a negati ve spi ke up to -VREG relati ve to PGND wi thout affecti ng operati on. Output gate dri ve for the swi tchi ng (top) MOSFET. Bootstrap pi n. A capaci tor i s connected between BST and D RN pi ns to develop the floati ng bootstrap voltage for the hi gh-si de MOSFET. The capaci tor value i s typi cally 1F (cerami c). Logi c level PWM i nput si gnal to the SC 1211 suppli ed by external controller. An i nternal 50kohm resi stor i s connected from thi s pi n to PGND . Vi rtual Phase Node. C onnect an RC between thi s pi n and the output sense poi nt to Enable C ombi -Sense TM operati on. See the Typi cal Appli cati on C i rcui t. Supply power for LD O and the i nternal C ombi -Sense converter.
TM
ci rcui try. C onnect to i nput power rai l of the
LD O output. D ecouple wi th 1F to 4.7F (cerami c) wi th lead length no more than 0.2" (5mm). Output gate dri ve for the synchronous (bottom) MOSFET. Ground. Keep thi s pi n close to the synchronous MOSFETs source.
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SC1211
POWER MANAGEMENT Block Diagram
VIN
LDO
VREG
UVLO
LOGIC
VPN
BST CONTROL & OVERLAP PROT ECTION CIRCUIT TG DRN
CO
PGND
BG
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SC1211
POWER MANAGEMENT Applications Information
THEORY OPERATION THEOR Y OF OPERATION The SC1211 is a high speed, Combi-SenseTM, dual output driver designed to drive top and bottom MOSFETs in a synchronous Buck converter. It features adaptive delay for shoot-through protection and VID-on-Fly operation; internal LDO for optimum gate drive voltage; and Virtual Phase Node for Combi-SenseTM solution. These drivers combined with PWM controller SC2643VX form a multi-phase voltage regulator for advanced microprocessors. A three-phase voltage regulator with 12V input 60A output is shown in the Typical Application Circuit section. Startup and UVLO To startup the driver, a supply voltage is applied to VIN pin of the SC1211. The top and bottom gates are held low until VIN exceeds UVLO threshold of the driver, typically 4.0V. Then the top gate remains low and the bottom gate is pulled high to turn on the bottom FET. Once VIN exceeds UVLO threshold of the PWM controller, typically 7.5V, the soft-start begins and the PWM signal takes fully control of the gate transitions. Gate Transition Shoot through Pro Gat e Transition and Shoo t thr ough Pr o t ection Refer to the Timing Diagrams section, the rising edge of the PWM input initiates the bottom FET turn-off and the top FET turn-on. After a short propagation delay (tPDL_BG), the bottom gate begins to fall (tF_BG). An adaptive circuit in the SC1211 monitors the bottom gate voltage to drop below 1.4V. Then after a preset delay time (tPDH_TG) is expired, the top gate turns on. The delay time is set to be 20ns typically. This prevents the top FET from turning on until the bottom FET is off. During the transition, the inductor current is freewheeling through the body diode of either bottom FET or top FET, upon the direction of the inductor current. The phase node could be low (ground) or high (VIN). The falling edge of the PWM input controls the top FET turn-off and the bottom FET turn-on. After a short propagation delay (tPDL_TG), the top gate begins to fall (tF_TG). As the inductor current is commutated from the top FET to the body diode of the bottom FET, the phase node begins to fall. The adaptive circuit in the SC1211 detects the phase node voltage. It holds the bottom FET off until the phase node voltage has dropped below 1.0V. This prevents the top and bottom FETs from conducting
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simultaneously or shoot-through. Minimum Off-Time for Bottom Gate During a load transient of the voltage regulator, the PWM controller could generate a very narrow pulse for the driver SC1211. The pulse is so narrow that it reaches the rising edge threshold of the SC1211 at one point then immediately falls below the falling edge threshold. To response such a PWM input, the bottom gate of the SC1211 has to pull down and pull up almost simultaneously, resulting in a voltage spike at the BG pin. The spike could exceed the gate voltage rating and damage the gate. To prevent such fast gate transition, a minimum off-time (typically 75ns) for the bottom gate is designed in the SC1211. When the PWM input reaches the rising edge threshold of the SC1211, the bottom gate pulls low and will stay low for the minimum off-time no matter what the PWM input at the CO pin is. VID-on-Fly Operation Certain new processors have required to changing the VID dynamically during the operation, or refered as VIDon-Fly operation. A VID-on-Fly can occur under light load or heavy load conditions. At light load, it could force the converter to sink current. Upon turn-off of the top FET, the reversed inductor current has to be freewheeling through the body diode of the top FET instead of the bottom FET. As a result, the phase node voltage remains high. The SC1211 incorporates the ability by pulling the bottom gate to high internally, which over rides the adaptive circuit and turns the bottom FET on. The delay time from the PWM falling egde to the bottom gate turn-on is set at 200ns typically. Virtual Phase Node for Combi-Sense TM Peak-Current-Mode control is widely employed in multiphase voltage regulators. It features phase current balance, fast transient response, and over current protection, etc. These are essential to low-voltage high-current regulators designed for advanced microprocessors. Usually, a costly current sensing resistor is required to obtain the output inductor current information for the peak current control. The Combi-SenseTM technique featured by the SC1211 is an approach to sense inductor current without using sensing resistor.
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SC1211
POWER MANAGEMENT Applications Information (Cont.)
VIN
VIN
Refer to Semtech SC2643VX Combi-Sense TM Current Mode Controller about the details of the Combi-Sense technique. Gate Drive Voltage Optimized Gat e Driv e V oltage
Lo Vout
Q1 Qcst VPN C DRN
Q2 Qcsb PGND + Co
Rcs
Ccs
SC1211
Inductor C urrent Signal
The above circuit shows the concept of Combi-SenseTM technique. An internal totem pole (Qcst, Qcsb) generates a VPN (Virtual Phase Node) signal. This VPN follows the DRN (or the Power Phase Node) with the same timing. A RC network (Rcs and Ccs) is connected between VPN and Vout. During Q1 turn-on, Qcst turns on as well. The voltage drop across Q1 and Lo charges Ccs. During Q2 turn-on, Qcsb turns on as well. The voltage drop across Q2 and Lo discharges Ccs. Both voltage drops are proportional to the inductor current and a resistance equal to FET's Rdson plus ESR of the inductor. If the time constant Rcs x Ccs is close to the Lo/Ro of the inductor, where Ro is given by
With the supply voltage in between 9V to 16V, an internal LDO is designed with the SC1211 to bring the voltage to a lower level for gate drive. An external Ceramic capacitor(1uF to 4.7uF) connected in between Vreg to ground is needed to support the LDO. The LDO output is connected to low gate drive internally, and has to be connected to high gate drive through an external bootstrap circuit. The LDO output voltage is set at 8.5V. The manufacture data and bench tested results show that, for low Rdson FETs run at applied load current, the optimum gate drive voltage is around 8.5V, where the total power losses of power FETs, including conduction loss and switching loss, are minimized. Thermal Shut Down The SC1211 will shut down by pulling both driver outputs low if its junction temperature, Tj, exceeds 155C. COMPONENT SELECTION MOSFETs Freq uency, Inductor requency Switching F req uency, Induct or and MOSFETs The SC1211 is capable of providing up to 3.5A peak drive current, and operating up to 1.5MHz PWM frequency without causing thermal stress on the driver. The selection of switching frequency, together with inductor and FETs is a trade-off between the cost, size, and thermal management of a multi-phase voltage regulator. In modern microprocessor applications, these parameters could be in the range of: Switching Frequency 100kHz to 500kHz per phase Inductor Value 0.2uH to 2uH FETs 4m-ohm to 20m-ohm Rdson 20nC to 100nC total gate charge Bootstrap Circuit The SC1211 uses an external bootstrap circuit to provide a voltage for the top FET drive. This voltage, referring to the Phase Node, is held up by a bootstrap capaci9 www.semtech.com
Ro = Rinductor + Rdson _ hs * D + Rdson _ ls * (1 - D)
the signal developed across Ccs will be proportional to the inductor current, where Ro is the equivalent current sensing resistance. In the above equation, Rinductor is ESR of the inductor, Rdson_hs and Rdson_ls are the top and bottom FET's Rdson, and D is the duty cycle of the converter. Since a perfect timing match down to the nanosecond is impossible, the VPN totem pole is held in tri-state during the communtations of DRN in the SC1211. This avoids errors and offset on the current detection which can be significant since the timing mismatch is multiplied by the input voltage. An optional capacitor between VPN and DRN allows these two nodes to be AC coupled during the tri-state window, hence yields a perfect timing match.
2003 Semtech Corp.
SC1211
POWER MANAGEMENT Applications Information (Cont.)
tor. The capacitor value can be calculated based on the total gate charge of the top FET, QTOP, and an allowed voltage ripple on the capacitor, VBST, in one PWM cycle: CBST > QTOP/VBST Typically, it is recommended to use a 1uF ceramic capacitor with 25V rating and a commonly available diode IN4148 for the bootstrap circuit. In addition, a small resistor (one ohm) has to be added in between DRN of the SC1211 and the Phase Node. The resistor is used to allievate the stress of the SC1211 from exposing to the negative spike at the Phase node. A negative spike could occur at the Phase Node during the top FET turn-off due to parasitic inductance in the switching loop. The spike could be minimized with a careful PCB layout. In those applications with TO-220 package FETs, it is recommended to use a clamping diode on the DRN pin to mitigate the impact of the excessive phase node negative spike. Filters for Supply Power For VREG pin of the SC1211, it is recommended to use a 1uF to 4.7uF, 25V rating ceramic capacitor for decoupling. LAY LAY OUT GUIDELINES The switching regulator is a high di/dt power circuit. Its Printed Circuit Board (PCB) layout is critical. A good layout can achieve an optimum circuit performance while minimized the component stress, resulting in better system reliability. For a multi-phase voltage regulator, the SC1211 driver, FETs, inductor, and supply decoupling capacitors in each phase have to be considered as a whole during PCB layout. Refer to Semtech SC2643VX/ SC1211 EVB Layout Guideline. For the SC1211 driver, the following guidelines are typically recommended during PCB layout: 1. Place the SC1211 close to the FETs for shortest gate drive traces and ground return paths. 2. Connect bypass capacitors as close as possible to decoupling pins (VREG and VIN) and PGND. The trace length of the decoupling capacitor on VREG pin should be no more than 0.2" (5mm).
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3. Locate the components of the bootstrap circuit close to the SC1211. CONSIDERATION SOLDERING CONSIDERATION The exposed die pad of the SC1211 is used for ground
Solder Pad
Solder Mask Copper Vias
return and thermal release of the driver. The pad must be soldered to the ground plane that is further connected to the system ground in the inner layer through multiple vias. For better electrical and thermal performance, it is recommended to use all copper available under the driver as the ground plane, and place the vias as close as possible to the solder pad. Meanwhile, the vias have to be masked out to prevent solder leakage during reflow. The layout arrangement is detailed in the above figure, which also can be found in the "Land Pattern - Power SOIC-8" section.
SC1211
POWER MANAGEMENT Outline Drawing - Power SOIC-8 Outline Drawing - Power SOIC-8L
Land Pattern - Power SOIC-8
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Rd., Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
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